1. Technical Field of the Invention
The present invention relates to semiconductor transmitting and receiving chips and, more particularly, to receivers in the receiving chips that are spread spectrum clocking tolerant.
2. Background Art
Spread spectrum clocking (SSC) has become ubiquitous in the personal computer industry for controlling electromagnetic emissions. FIG. 1 illustrates a typical SSC scheme in which the frequency of a clock signal changes in a triangular waveform between a maximum frequency (fmax) and a minimum frequency (fmin) that is equal to 0.995 fmax. The frequency of triangular waveform is typically about 30 kHz. However, fmax is many times greater (e.g., 100 MHz or higher).
In desktop personal computers, where common clock architectures dominate, the impact of SSC is minimal and, currently, no design changes are generally required to reap electromagnetic interference (EMI) benefit from SSC, which may be any where up to around 20 dB. Accordingly, almost all personal computer systems shipped today have SSC implemented.
In some computer systems and communications devices and systems, a clock is embedded in the data for input/output (I/O) or other signals. An example of a data signal with an embedded clock is one using the 8b/10b (8-bit/10-bit) coding scheme. A receiver including a receiving gate that gates the data signal to produce a gated data signal. The receiver also include clock recovery circuitry to extract clock information to create a signal to clock the receiving gate. To date, SSC proliferation in embedded clock systems has been limited due to the inability of present receivers to track the kHz modulation frequency variations. That is, the receivers have difficulty differentiating between deliberate frequency changes and unintentional jitter on the clock. An example of such a receiver is an interpolator based receiver. In some interpolator based receivers, a local reference clock is used in conjunction with the embedded clock information to determine the optimum timing for gating data.
For example, FIG. 2 illustrates a prior art system 10 in which a transmitting chip 14 transmits a data signal with embedded clock information to a receiving chip 16 over an interconnect 18. The clock information may be embedded through a coding technique such as 8b/10b or some other technique. Transmitter 22, in transmitting chip 14, transmits the data signal in response to a transmitting clock signal that has a constant frequency rather than SSC. Transmitter 22, interconnect 18, and an interpolator based receiver 24 in receiving chip 16 may form a point to point serial link. Receiver 24 includes a receiving gate 26 and clock recovery circuitry 28. In the example of FIG. 2, the clock recovery circuitry 28 includes a phase detector 32 (for example, an edge detector) and a phase interpolator 30. Receiving gate 26 receives the data signal on interconnect 18 and a clock signal from phase interpolator 30 referred to herein as the “in phase clock signal” because it is in phase with the data signal on interconnect 18. The in phase clock signal gates receiving gate 26 to produce the gated data signal from the data signal on interconnect 18.
Phase detector 32 analyzes the data signal on interconnect 18 to extract phase information regarding the data signal. The phase information is included in a phase information signal provided to phase interpolator 30. A local reference source 34 provides a reference clock signal which has a frequency which is very close (and ideally identical) to the frequency of the transmitting clock signal provided to transmitter 22. Phase interpolator 30 creates the in phase clock signal through using the reference clock signal from local reference source 34 and the phase information signal from phase detector 32.
As noted, the transmitting clock signal applied to transmitter 22 has a constant frequency. (Of course, there is some unintended jitter in the clock.) If instead, a SSC clock, were applied to transmitter 22, interpolator 30 would not, in many cases, be able to differentiate between the deliberate frequency movement of SSC and the unintentional jitter on the clock. Accordingly, the in phase clock signal would not always actually be in phase and some of the data signal would not be gated at a correct time.
There are various ways in which to implement an interpolator based receiver such as the one shown in system 10 of FIG. 2. It takes time for phase detector 32 and phase interpolator 30 to perform their functions. Under one approach, there is a delay in receiving gate 26 so that the portion of the data signal that is being gated is gated by an in phase clock signal generated through phase interpolator 30 and phase detector 32 in response to the same portion of the data signal. Under another approach, there is no delay or just a slight delay so that a portion of the data signal is gated in response to a portion of the in phase clock signal generated in response to a previous portion of the data signal. This is not a problem since the phase of the data signal rarely would change much over such a short amount of time. The phase detector 32 might merely sample some portions of the data signal. Other control circuitry can be used in connection with, for example, test patterns to obtain or retain the in phase clock signal. In some implementations, the edge detector receives data from the output of receiving gate 26 rather than at the input.